For institutions

Write Verilog and see the waveform in your browser.

Write a module, run it, and read the simulated waveform next to your code. Testbench checks tell you whether the design behaves before you move on. Nothing to install.

Start free
counter.vExample
module counter (
    input  wire       clk,
    input  wire       rst,
    output reg  [3:0] count
);
    always @(posedge clk) begin
        if (rst) count <= 4'd0;
        else     count <= count + 4'd1;
    end
endmodule

Simulated output after Run

clkrstcountx0123456

Simulators are hard to set up. Waveforms are hard to read alone.

Most students meet HDL through a lab machine with a licensed tool, or a local install that takes an afternoon to get working. Practice stops when the lab closes.

Lab0 runs the simulator for you. You write the module, press Run, and see the compiler output and the waveform in the same window, so you can connect each line of code to the signal it drives.

What you’ll practise

  • Combinational logic

    Gates, multiplexers, decoders and adders described with continuous assignments.

  • Sequential logic

    Flip-flops, registers and counters driven by a clock and reset.

  • Finite state machines

    State encoding, next-state logic and output logic for controllers.

  • Testbenches

    Drive inputs, check outputs and read the result in the waveform.

How your work is checked

When you submit, a testbench drives your module and checks its outputs cycle by cycle. A failing check tells you which cycle went wrong and what was expected.

counter.vExample
  • reset clears count to 0Passed
  • count increments on each rising edgePassed
  • count stays 0 while rst is highPassed
  • count wraps from 15 to 0Failedcycle 17: expected count = 0, got 16. count is declared 5 bits wide; the spec asks for 4.

3 of 4 checks passed

For departments

Electronics and electrical departments can run HDL labs and timed exams in the browser, with every submission checked automatically.

Book a pilot call

Questions

Do I need to install a simulator?

No. Your code is compiled and simulated with Icarus Verilog on Lab0's servers. The output and the waveform appear in your browser.

Can I use SystemVerilog?

The simulator runs Icarus Verilog with IEEE 1800-2012 support enabled, so many SystemVerilog constructs work. Icarus does not support the full language.

Can my college use this for lab exams?

Yes. Colleges can run timed, proctored assessments in the Lab0 secure browser and see results for each class.